1. Field of the Invention
The present invention relates to a solid state imaging device having a vertical overflow drain structure for preventing blooming.
2. Description of the Related Art
There is an upper limit to a charge quantity which each pixel can treat in a solid state imaging device, irrespective of its type such as CCD and MOS. For this reason, when each pixel receives excess light, charge overflows each pixel into the surrounding pixels, resulting in blooming. In order to prevent blooming, it has been proposed to provide an overflow drain structure at a photodetecting portion of the solid state imaging device so as to absorb charge which exceeds a threshold value. In recent years, a vertical overflow drain structure, which can avoid the decrease in the ratio of opening of pixels, has widely been utilized.
FIG. 7 shows a vertical overflow drain structure used in a CCD imaging device of an interline transfer type. In this figure, the structure for one pixel is schematically shown; and a vertical direction represents a depth of a device and a horizontal direction represents a direction orthogonal to a transfer direction of a vertical transfer portion. This CCD imaging device is of a conductive type using electrons as a signal charge.
Referring to FIG. 7, a p-well layer 2 is formed on an n-type semiconductor substrate 1. In part of the upper portion of the p-well layer 2, a photodetecting portion 3 made of an n-type semiconductor is formed so as to receive light for one pixel. In addition, the upper surface of the photodetecting portion 3 is covered with a high concentration p-type semiconductor layer 4. On one side of the photodetecting portion 3, a channel stop region 5 is formed. On the other side thereof, a buried channel type transfer portion 7 made of an n-type semiconductor is formed with a transfer region 6 (part of the p-well layer 2) sandwiched between the transfer portion 7 and the photodetecting portion 3. The channel stop region 5 functions as a partition between the respective pixels. The transfer region 6 regulates the conduction between the photodetecting portion 3 and the transfer portion 7 by using an electrical potential barrier. The electrical potential of the transfer portion 7 is regulated by an electrode 8 formed above the transfer portion 7, an insulating layer (not shown) being formed between the transfer portion 7 and the electrode 8.
The semiconductor substrate 1 is applied with a sufficiently high positive voltage, which is a reverse bias with respect to a channel stop electrical potential (earth electrical potential, i.e., 0 V). When excess light is incident upon the photodetecting portion 3 and a great amount of electrons are accumulated therein, electrons overflow from the photodetecting portion 3 into the reversely biased semiconductor substrate 1 beyond an electrical potential barrier formed by the p-well layer 2. Thus, blooming can be prevented.
FIG. 8 shows a distribution of impurity concentration on a B--B section of the CCD imaging device of FIG. 7. For simplicity, the impurity concentration is approximately represented in a step form. The semiconductor substrate 1 has an impurity concentration of N.sub.1 ; the p-well layer 2 has a thickness of d.sub.2 and an impurity concentration of N.sub.2 ; the photodetecting portion 3 has a thickness of d.sub.3 and an impurity concentration of N.sub.3 ; and the semiconductor layer 4 has a thickness of d.sub.4 and an impurity concentration of N.sub.4.
Assuming that the maximum potential of the photodetecting portion 3 is V.sub.A ; a height of a potential barrier from the photodetecting portion 3 to the semiconductor substrate 1 is V.sub.B ; a height of a potential barrier from the semiconductor substrate 1 to the photodetecting portion 3 is V.sub.C ; a distance from the boundary between the semiconductor layer 4 and the photodetecting portion 3 to the depth of the photodetecting portion 3 where the maximum potential thereof is obtained; and a distance from the boundary between the p-well layer 2 and the photodetecting portion 3 to the depth of the photodetecting portion 3 where the maximum potential thereof is obtained are a and b, respectively, the following Equation (1) can be obtained. ##EQU1## where q: prime charge,
K.sub.s : a relative dielectric constant of a semiconductor, PA1 .epsilon..sub.o : a dielectric constant of a vacuum PA1 V.sub.A =7.13 V, PA1 V.sub.sub =28.53 V PA1 V.sub.C =21.40 V PA1 a semiconductor substrate of a first conductive type; PA1 a well layer made of a semiconductor of a second conductive type formed on the semiconductor substrate; PA1 a photodetecting portion made of a semiconductor of the first conductive type formed in an upper portion of the well layer; PA1 a high concentration semiconductor layer made of the second conductive type formed in an upper portion of the photodetecting portion; PA1 a first region of the first conductive type formed in an upper portion of the semiconductor substrate, being in contact with the well layer and positioned at least below the photodetecting portion, having higher concentration than the semiconductor substrate; and PA1 a second region of the second conductive type formed in a lower portion of the well layer, being in contact with the semiconductor substrate and positioned on the first region.
A substrate voltage V.sub.sub to be applied to the semiconductor substrate 1 is represented by the following Equation (2): EQU V.sub.sub =V.sub.A -V.sub.B +V.sub.C ( 2)
The CCD imaging device will be described with reference to FIG. 9, where the respective impurity concentrations are N.sub.1 =2.times.10.sup.14 cm.sup.-3, N.sub.2 =1.times.10.sup.15 cm.sup.-3, N.sub.3 =2.times.10.sup.16 cm.sup.-3, and N.sub.4 =1.times.10.sup.18 cm.sup.-3 ; the respective layer thicknesses are d.sub.3 =0.672 .mu.m and d.sub.2 =2.148 .mu.m; and the respective voltages at the time of depletion (electrons are not accumulated in the photodetecting portion 3) are V.sub.A =6 V, V.sub.B =1 V, and V.sub.C =5 V.
At the time of depletion, the substrate voltage V.sub.sub becomes 10 V according to Equation (2). As shown in FIG. 9, the height of the potential barrier V.sub.B and the height of the potential barrier V.sub.C become appropriate values, so that electrons can be accumulated in the photodetecting portion 3.
When the electrons are accumulated in the photodetecting portion 3 up to charge Q.sub.S (representing a level of a saturated signal) and the height of the potential barrier V.sub.B decreases to V.sub.B0 under the condition that the substrate voltage V.sub.sub is retained, the electrons are increased to overflow into the semiconductor substrate 1 and the current is increased to an overflow current I.sub.OF. Thus, blooming can be prevented. The height of the potential barrier V.sub.B0 is about 0.5 V in the case of a silicon semiconductor device. Assuming that the distances a and b obtained from Equations (1) and (2) are a.sub.0 and b.sub.0, respectively, the charge Q.sub.S is represented by the following Equation (3): EQU Q.sub.S =(d.sub.3 -a.sub.0 -b.sub.0)N.sub.3 ( 3)
The following maximum potential V.sub.A, height of the potential barrier V.sub.B, substrate voltage V.sub.sub, and charge Q.sub.S are respectively obtained based on the above. EQU V.sub.A =1.88 V, V.sub.sub =10.00 V EQU V.sub.C =8.62 V, Q.sub.S =5.76.times.10.sup.11 cm.sup.-2
This corresponds to a state of overflow shown in FIG. 9.
In addition, when the substrate voltage V.sub.sub is increased under the condition that electrons are not accumulated in the photodetecting portion 3, the height of the potential barrier V.sub.B is decreased. When the height of the potential barrier V.sub.B becomes 0, the potential distribution of the CCD imaging device regularly increases in the depth direction and the electrons are completely discharged into the semiconductor substrate 1 without being accumulated in the photodetecting portion 3. Thus, an electron shutter function regulating an effective accumulation time of electrons in the photodetecting portion 3 can be obtained by increasing the substrate voltage V.sub.sub to a higher level. In this case, the distances a and b become 0 and d.sub.3, respectively. Assuming that the maximum potential V.sub.A and the height of the potential barrier V.sub.C obtained from Equation (1) are V.sub.AS and V.sub.CS, respectively, the substrate voltage V.sub.sub can be represented by the following Equation (4): EQU V.sub.sub (Sh)=V.sub.AS +V.sub.CS ( 4)
The following maximum potential V.sub.A, the height of the potential barrier V.sub.C, and substrate voltage V.sub.sub are respectively obtained based on the above.
This corresponds to a state of shutter shown in FIG. 9.
As a result, in the vertical type overflow drain structure shown in FIG. 7, it is required to apply an extremely high voltage to the semiconductor substrate 1 (i.e., the substrate voltage V.sub.sub : 10 V during ordinary operation and 28.53 V during shutter operation. Such a high voltage provides a drive circuit of a solid state imaging device with a great burden, so that it has been suggested that the substrate voltage V.sub.sub is decreased (Japanese Laid-Open Patent Publication No. 62-24666).
A vertical type overflow drain structure which is capable of decreasing the substrate voltage V.sub.sub is shown in FIG. 10. In this structure, a first region 10 is formed in the upper portion of the n-type semiconductor substrate 1 so as to be in contact with the p-well layer 2. In the horizontal direction, the first region 10 is formed in a region below the photodetecting portion 3. In the first region 10, the impurity concentration is higher than that of the p-well layer 2.
When the first region 10 is formed in the semiconductor substrate 1, as shown in FIG. 11, the impurity concentration in a portion of the semiconductor substrate 1 in contact with the p-well layer 2 is N.sub.10 which is higher than N.sub.1. Assuming that the impurity concentration N.sub.10 is 3.times.10.sup.15 cm.sup.-3 under the conditions that N.sub.1 =2.times.10.sup.14 cm.sup.-3, N.sub.2 =1.times.10.sup.15 cm.sup.-3, N.sub.3 =2.times.10.sup.16 cm.sup.-3, N.sub.4 =1.times.10.sup.18 cm.sup.-3, d.sub.3 =0.672 .mu.m, d.sub.2 =2.148 .mu.m, V.sub.A =6 V, V.sub.B =1 V, and V.sub.C =5 V, the maximum potential V.sub.A of the photodetecting portion 3, the height of the potential barrier V.sub.C thereof, substrate voltage V.sub.sub, and charge Q.sub.S at the time of overflow become 1.88 V, 1.92 V, 3.29 V, and 5.76.times.10.sup.11 cm.sup.-2. Under the same conditions as these, the maximum potential V.sub.A of the photodetecting portion 3, height of the potential barrier V.sub.C thereof, and substrate voltage V.sub.sub at the time of shutter become 7.13 V, 4.76 V, and 11.89 V.
FIG. 12 shows a distribution of impurity concentration on a C--C section of the CCD imaging device of FIG. 10. In the electrical potential distribution at the time of overflow and that at the time of shutter shown in this figure, an overflow current I.sub.OF can be discharged into the semiconductor substrate 1 at the time of overflow and all of the electrons accumulated in the photodetecting portion 3 can be discharged into the semiconductor substrate 1 at the time of shutter. In addition, the substrate voltage V.sub.sub can greatly be decreased in the respective cases.
In the above examples, the maximum potential V.sub.A, the height of the potential barrier V.sub.B, the height of the potential barrier V.sub.C, and the substrate voltage V.sub.sub at the time of depletion become 5.46 V, 2.37 V, 0.20 V, and 3.29 V. Thus, under this condition, the maximum potential V.sub.A becomes higher than the substrate voltage V.sub.sub. In addition, the height of the potential barrier V.sub.C becomes as small as 0.20 V. As is apparent from the potential distribution at the time of depletion shown in FIG. 12, electrons are injected from the semiconductor substrate 1 into the photodetecting portion 3.
Because of this, in the conventional overflow drain structure shown in FIG. 10, for practical use, it is required to make the substrate voltage V.sub.sub higher than the above example. Otherwise, the effects that the substrate voltage V.sub.sub is greatly decreased to alleviate the burden of the drive circuit of the solid state imaging device cannot sufficiently be obtained. In addition, in the above example, there arise problems that the height of the potential barrier V.sub.B becomes extremely small and the signal charge is hardly accumulated in the photodetecting portion 3.